The present disclosure relates to a semiconductor memory device, and more particularly, to a clock pulse generating circuit.
After performing a read operation, double data rate synchronous dynamic random access memory (DDR SDRAM) outputs a DQ strobe signal and a DQ data signal to a DQS pin and a DQ pin, respectively, under a predetermined timing condition associated with a system clock. The timing condition is that toggle points of the DQ strobe signal and the DQ data signal output from the DDR SDRAM should be concurrent with that of the external system clock, or a time difference therebetween, if any, should be within a predetermined range.
The timing condition can be satisfied with the help of an internal delay locked loop (DLL) of a DRAM, which is configured to generate a DLL clock imitating the external system clock. A rising clock signal RCLKDLL and a falling clock signal FCLKDLL, which imitate a rising and a falling of the clock, respectively, are important factors in determining tAC and tDQSCK.
A skew may be generated between the signals RCLKDLL and FCLKDLL depending on routing rules and operation conditions. Thus deterioration of the characteristics such as tAC and tDQSCK may be caused depending on a circuit type of a DQ driver which receives the signals RCKDLL and FCKDLL.
FIG. 1 illustrates a block diagram of a conventional circuit for generating a DQ data driving signal.
Referring to FIG. 1, signals RCLKDLL and FCLKDLL are output from a DLL 300 to be input into pre-drivers 200 of a respective DQ after passing through a pulse generator 100.
Cycles of the signals RCLKDLL and FCLKDLL are 1×tCK and time intervals for maintaining each logic level state thereof are ½×tCK.
Time intervals for maintaining each logic level state of the signals RCLKDO and FCLKDO output from the pulse generator 100 are tPW, whereas cycles thereof are the same as those of the signals RCLKDLL and FCLKDLL.
FIG. 2 illustrates a circuit diagram of a conventional pulse generator.
Referring to FIG. 2, a pulse generator 100 receives the signals RCLKDLL and FCLKDLL and reduces pulse widths thereof to output signals RCLKDO and FCLKDO. For example, when cycles and time intervals for maintaining each logic level state of the signals RCLKDLL and FCLKDLL are 1×tCK and ½×tCK, respectively, those of the signals RCLKDO and FCLKDO are 1*tCK and tPW, respectively. The time tPW is determined by a signal of node A and a signal of node B, the signal of node B being generated by delaying and inverting the received signals RCLKDLL and FCLKDLL.
FIG. 3 illustrates an operation waveform generated by the conventional pulse generator of FIG. 2, when a low frequency signal is input. FIG. 4 illustrates an operation waveform generated by the conventional pulse generator of FIG. 2, when a high frequency signal is input.
Referring to FIGS. 3 and 4, the pulse generator generates pulse signals RCLKDO and FCLKDO having pulse widths of tPW. However, it is not true when the frequencies of the input signals RCLKDLL and FCLKDLL are high, i.e., when ½×tCK is smaller than tPW. Instead, in such case, output signals from the pulse generator have cycles of 1*tCK and pulse widths of ½*tCK which is smaller than tPW.
In other words, when frequencies of the input signals are higher than a predetermined frequency, the pulse generator generates a level-type signal, not a pulse.
FIG. 5 illustrates a circuit diagram of a conventional pre-driver. A pre-driver 200 assigned to each DQ has a circuit for synchronizing a data signal with signals RCLKDO and FCLKDO and outputting the synchronized data signal to the DQ driver.
In general, the pre-driver may show a stable operation when signals RCLKDO and FCLKDO generated by low frequency signals (signals having ½×tCK greater than tPW) are input thereinto. That is, the signals RCLKDO and FCLKDO do not have overlap regions where both of them have logic high levels at a same time when a data signals is transferred. Accordingly, the pre-driver may easily distinguish the rising clock and the falling clock.
However, when the input signals are of high frequencies, i.e., when the input signals have ½*tCK smaller than tPW, the pulse generator may not generate signals RCLKDO and FCLKDO having pulse widths of tPW. Level-type signals having logic high levels for time intervals of ½×tCK are generated, instead. Such signals may be overlapped in the pre-driver.
Granting that overlap regions are not generated, a turn-on region may be generated at regions where the logic levels of the signals changes from logic high level to logic low level or from logic low level to logic high level.
Accordingly, during the synchronization of a data signal with signals RCLKDO and FCLKDO in a pre-driver, deterioration of characteristics may be caused for as long time as the overlap regions of a logic high level. Characteristics such as tAC and tDQSCK may also be deteriorated in a DQ driver.